SH7670 Datasheet, PDF (549/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
14.2.13 FEC DMAC Processing Descriptor Start Address Register (FECDSA)
Do not write any value to this register when FECC_E is set to 1.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FECDSA[31:16]
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
FECDSA[15:4]
FECDSA[3:0]
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
R
R
R
Bit
31 to 4
3 to 0
Bit Name
Initial
Value R/W
FECDSA[31:4] All 0 R/W
FECDSA[3:0] All 0 R
Description
Descriptor Ring Start Address
Specify a descriptor ring start address. Set a 16-byte
boundary address value.
Rev. 1.00 Nov. 14, 2007 Page 523 of 1262
REJ09B0437-0100