SH7670 Datasheet, PDF (595/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 15 Stream Interface (STIF)
Table 15.3 PLL Lock Threshold Value
Bits 11 to 8
Description
LKCYC3 to
LKCYC0
PLL Lock Threshold
Value
(× PWM Reference
Clock)
Acceptable
Acceptable Comparison (Internal
Comparison STC - Internal PCR)
Bit Count n Result Range *¹
PWM Control
Variable*²
(ILGL = 1)
0000
2
0


0001
4
1
–1 to +1
–2
0010
8
2
–3 to +3
–4
0011
16
3
–7 to +7
–8
0100
32
4
–15 to +15
–16
0101
64
5
–31 to +31
–32
0110
128
6
–63 to +63
–64
0111
256
7
–127 to +127
–128
1000
512
8
–255 to +255
–256
1001
1024
9
–511 to +511
–512
1010
2048
10
–1023 to +1023
–1024
1011
4096
11
–2047 to +2047
–2048
1100
8192
12
–4095 to +4095
–4096
1101
16384
13
–8191 to +8191
–8192
1110
32768
14
–16383 to +16383
–16384
1111
65536
15
–32767 to +32767
–32768
Notes: 1. When the comparison (internal STC - internal PCR) result falls within the acceptable
comparison result range, the LKZF bit is set to 0.
2. If the PWM control variable is -(2^n), it is treated as an invalid PWM control variable
(ILGL = 1) and the LKZF bit is set to 1. The PWM control variable is selected by the
PWMSEL and PWMSEL2 bits.
Rev. 1.00 Nov. 14, 2007 Page 569 of 1262
REJ09B0437-0100