SH7670 Datasheet, PDF (927/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 20 Host Interface (HIF)
20.7 External DMAC Interface
Figures 20.7 to 20.10 show the HIFDREQ output timing. The start of the HIFDREQ assert
synchronizes with the DTRG bit in HIFDTR being set to 1. The HIFDREQ negate timing and
assert level are determined by the DMD and DPOL bits in HIFSCR, respectively.
When the external DMAC is specified to detect low level of the HIFDREQ signal, set DMD = 0
and DPOL = 0. After writing 1 to the DTRG bit, the HIFDREQ signal remains low until a read
from or write to the HIFIDX-specified register is detected. Writing to the index register (HIFIDX)
does not negate the signal.
DTRG bit
DPOL bit
HIFDREQ
HIFCS
HIFRS
Asserted in synchronization with the
DTRG bit being set by the on-chip CPU.
The DTRG bit is cleared
simultaneously with
HIFDREQ negate.
Negated if a read from or write to the HIFIDX-specified register is detected.
The latency is within tpcyc (cycle of the peripheral clock) × 5CYC.
Figure 20.7 HIFDREQ Timing (When DMD = 0 and DPOL = 0)
When the external DMAC is specified to detect high level of the HIFDREQ signal, set DMD = 0
and DPOL = 1. At the time the DPOL bit is set to 1, HIFDREQ becomes low. After this, the
HIFDREQ signal remains low from when 1 is written to the DTRG bit until a read from or write
to the HIFIDX-specified register is detected. Writing to the index register (HIFIDX) does not
negate the signal.
DTRG bit
DPOL bit
Negated in synchronization
with the DPOL bit being set
by the on-chip CPU.
HIFDREQ
HIFCS
HIFRS
Asserted in synchronization
with the DTRG bit being set
by the on-chip CPU.
The DTRG bit is cleared
simultaneously with
HIFDREQ negate.
Negated if a read from or write to the HIFIDX-specified register is detected.
The latency is within tpcyc (cycle of the peripheral clock) × 5CYC.
Figure 20.8 HIFDREQ Timing (When DMD = 0 and DPOL = 1)
Rev. 1.00 Nov. 14, 2007 Page 901 of 1262
REJ09B0437-0100