SH7670 Datasheet, PDF (394/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 10 Watchdog Timer (WDT)
(2) Writing to WRCSR
WRCSR must be written by a word access to address H'FFFE0004. It cannot be written by byte
transfer or longword transfer instructions.
Procedures for writing 0 to WOVF (bit 7) and for writing to RSTE (bit 6) are different, as shown
in figure 10.3.
To write 0 to the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower
byte. This clears the WOVF bit to 0. The RSTE bit is not affected. To write to the RSTE bit, the
upper byte must be H'5A and the lower byte must be the write data. The value of bit 6 of the lower
byte is transferred to the RSTE bit, respectively. The WOVF bit is not affected.
Writing 0 to the WOVF bit
15
87
0
Address: H'FFFE0004
H'A5
H'00
Writing to the RSTE and RSTS bits
15
Address: H'FFFE0004
H'5A
87
0
Write data
Figure 10.3 Writing to WRCSR
(3) Reading from WTCNT, WTCSR, and WRCSR
WTCNT, WTCSR, and WRCSR are read in a method similar to other registers. WTCSR is
allocated to address H'FFFE0000, WTCNT to address H'FFFE0002, and WRCSR to address
H'FFFE0004. Byte transfer instructions must be used for reading from these registers.
Rev. 1.00 Nov. 14, 2007 Page 368 of 1262
REJ09B0437-0100