SH7670 Datasheet, PDF (223/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 7 Bus State Controller (BSC)
(2) SDRAM
• CS3WCR
Bit: 31 30 29 28 27 26 25 24 23 22
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
-
WTRP[1:0]
-
WTRCD[1:0]
-
A3CL[1:0]
-
Initial value: 0
0
0
0
0
1
0
1
0
0
R/W: R R/W R/W R R/W R/W R R/W R/W R
21 20 19 18 17 16
-
-
-
-
-
-
0
0
0
0
0
0
R
R
R
R
R
R
5
4
3
2
1
0
-
TRWL[1:0]
-
WTRC[1:0]
0
0
0
0
0
0
R R/W R/W R R/W R/W
Bit
31 to 15
14, 13
Bit Name

WTRP[1:0]
Initial
Value R/W Description
All 0 R
Reserved
These bits are always read as 0. The write value
should always be 0.
00
R/W Number of Auto-Precharge Completion Wait Cycles
Specify the number of minimum precharge completion
wait cycles as shown below.
• From the start of auto-precharge and issuing of
ACTV command for the same bank
• From issuing of the PRE/PALL command to issuing
of the ACTV command for the same bank
• Till entering the power-down mode or deep power-
down mode
• From the issuing of PALL command to issuing REF
command in auto refresh mode
• From the issuing of PALL command to issuing
SELF command in self refresh mode
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
Rev. 1.00 Nov. 14, 2007 Page 197 of 1262
REJ09B0437-0100