SH7670 Datasheet, PDF (701/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
17.3.15 SOF Control Register (SOFCFG)
SOFCFG is a register that specifies the transaction-enabled time and BRDY interrupt status clear
timing.
This register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
TRNEN
SEL
—
BRDYM
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0* 0
0
0
0
0
R/W: R
R
R
R
R
R
R R/W R R/W R
R
R
R
R
R
Bit
Bit Name
15 to 9 
Initial
Value
All 0
8
TRNENSEL 0
7

0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Transaction-Enabled Time Select
Selects the transaction-enabled time either for full- or
low-speed communication, where is the time in which
this module issues tokens in a frame via the port.
0: For non-low-speed communication
1: For low-speed communication
This bit is valid only when the host controller function
is selected. Even when the host controller function is
selected, the setting of this bit has no effect on the
transaction-enabled time during high-speed
communication.
This bit should be set to 0 when the function
controller function is selected.
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 14, 2007 Page 675 of 1262
REJ09B0437-0100