SH7670 Datasheet, PDF (903/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 20 Host Interface (HIF)
20.2 Input/Output Pins
Table 20.1 shows the HIF pin configuration.
Table 20.1 Pin Configuration
Name
Abbreviation
I/O Description
HIF data pins
HIF chip select
HIFD15 to HIFD00 I/O
HIFCS
Input
Address, data, or command input/output to the
HIF
Chip select input to the HIF
HIF register select HIFRS
Input Switching between HIF access types
0: Normal access (other than below)
1: Index register write
HIF write
HIF read
HIF interrupt
HIFWR
HIFRD
HIFINT
Input Write strobe signal. Low level is input when an
external device writes data to the HIF.
Input Read strobe signal. Low level is input when an
external device reads data from the HIF.
Output Interrupt request to an external device from the
HIF
HIF mode
HIFMD
Input
Selects whether or not this LSI is started up in
HIF boot mode. If a power-on reset is canceled
when high level is input, this LSI is started up in
HIF boot mode.
HIFDMAC transfer HIFDREQ
request
Output To an external device, DMAC transfer request
with HIFRAM as the destination
HIF boot ready
HIFRDY
Output Indicates that the HIF reset is canceled in this
LSI and access from an external device to the
HIF can be accepted.
After 20 clock cycles (max.) of the peripheral
clock following negate of the reset input pin of
this LSI, this pin is asserted.
HIF pin enable
HIFEBL
Input All HIF pins other than this pin are asserted by
high-level input.
Rev. 1.00 Nov. 14, 2007 Page 877 of 1262
REJ09B0437-0100