SH7670 Datasheet, PDF (317/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 7 Bus State Controller (BSC)
In a write cycle for the cache-enabled space, the write cycle operation differs according to the
cache write methods.
In write-back mode, the cache is first searched. If data is detected at the address corresponding to
the cache, the data is then re-written to the cache. In the actual memory, data will not be re-written
until data in the corresponding address is re-written. If data is not detected at the address
corresponding to the cache, the cache is modified. In this case, data to be modified is first saved to
the internal buffer, 16-byte data including the data corresponding to the address is then read, and
data in the corresponding access of the cache is finally modified. Following these operations, a
write-back cycle for the saved 16-byte data is executed.
In write-through mode, the cache is first searched. If data is detected at the address corresponding
to the cache, the data is re-written to the cache simultaneously with the actual write via the internal
bus. If data is not detected at the address corresponding to the cache, the cache is not modified but
an actual write is performed via the internal bus.
Since the bus state controller (BSC) incorporates a one-stage write buffer, the BSC can execute an
access via the internal bus before the previous external bus cycle is completed in a write cycle. If
the on-chip module is read or written after the external low-speed memory is written, the on-chip
module can be accessed before the completion of the external low-speed memory write cycle.
In read cycles, the CPU is placed in the wait state until read operation has been completed. To
continue the process after the data write to the device has been completed, perform a dummy read
to the same address to check for completion of the write before the next process to be executed.
The write buffer of the BSC functions in the same way for an access by a bus master other than
the CPU such as the DMAC. Accordingly, to perform dual address DMA transfers, the next read
cycle is initiated before the previous write cycle is completed. Note, however, that if both the
DMA source and destination addresses exist in external memory space, the next write cycle will
not be initiated until the previous write cycle is completed.
Changing the registers in the BSC while the write buffer is operating may disrupt correct write
access. Therefore, do not change the registers in the BSC immediately after a write access. If this
change becomes necessary, do it after executing a dummy read of the write data.
In this LSI, the priority level applicable when there is a request for bus mastership for the internal
bus from any of the internal bus masters excluding the CPU (that is, A-DMAC (including F-
DMAC), E-DMAC, and DMAC) can be set in the register.
When changing the priority level, rewrite the register after making sure that none of the A-DMAC
(including F-DMAC), E-DMAC, and DMAC is started.
Rev. 1.00 Nov. 14, 2007 Page 291 of 1262
REJ09B0437-0100