SH7670 Datasheet, PDF (24/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

23.1.11
23.1.12
23.1.13
23.1.14
Port F I/O Register L (PFIORL) ..................................................................... 1026
Port F Control Registers L2 and L1 (PFCRL2, PFCRL1) .............................. 1027
Port G I/O Registers H and L (PGIORH, PGIORL)....................................... 1031
Port G Control Registers H2, L2, and L1 (PGCRH2, PGCRL2, PGCRL1) ... 1032
Section 24 I/O Ports......................................................................................... 1039
24.1 Port A.............................................................................................................................. 1039
24.1.1 Register Descriptions...................................................................................... 1039
24.1.2 Port A Data Register H (PADRH) .................................................................. 1040
24.2 Port B.............................................................................................................................. 1042
24.2.1 Register Descriptions...................................................................................... 1042
24.2.2 Port B Data Register L (PBDRL) ................................................................... 1043
24.3 Port C.............................................................................................................................. 1045
24.3.1 Register Descriptions...................................................................................... 1045
24.3.2 Port C Data Registers H and L (PCDRH and PCDRL) .................................. 1046
24.4 Port D.............................................................................................................................. 1049
24.4.1 Register Descriptions...................................................................................... 1049
24.4.2 Port D Data Register L (PDDRL)................................................................... 1050
24.5 Port E .............................................................................................................................. 1052
24.5.1 Register Descriptions...................................................................................... 1052
24.5.2 Port E Data Register L (PEDRL).................................................................... 1053
24.6 Port F .............................................................................................................................. 1055
24.6.1 Register Descriptions...................................................................................... 1055
24.6.2 Port F Data Register L (PFDRL) .................................................................... 1056
24.7 Port G.............................................................................................................................. 1058
24.7.1 Register Descriptions...................................................................................... 1059
24.7.2 Port G Data Registers H and L (PGDRH and PGDRL).................................. 1059
Section 25 User Break Controller (UBC)........................................................ 1063
25.1 Features........................................................................................................................... 1063
25.2 Register Descriptions...................................................................................................... 1065
25.2.1 Break Address Register (BAR)....................................................................... 1066
25.2.2 Break Address Mask Register (BAMR) ......................................................... 1067
25.2.3 Break Data Register (BDR) ............................................................................ 1068
25.2.4 Break Data Mask Register (BDMR)............................................................... 1069
25.2.5 Break Bus Cycle Register (BBR) ................................................................... 1070
25.2.6 Break Control Register (BRCR) ..................................................................... 1072
25.3 Operation ........................................................................................................................ 1074
25.3.1 Flow of the User Break Operation .................................................................. 1074
25.3.2 Break on Instruction Fetch Cycle ................................................................... 1075
Rev. 1.00 Nov. 14, 2007 Page xxiv of xxvi