SH7670 Datasheet, PDF (594/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 15 Stream Interface (STIF)
Initial
Bit
Bit Name Value R/W Description
15
GAIN3
0
14
GAIN2
0
13
GAIN1
0
12
GAIN0
0
R/W These bits are used to control the right-shift amount that
R/W ^{gains the error amount to be input to the adder from}
selector 1. Since the error amount is expressed as a two's
R/W _{complement, an arithmetic shift is used for right shift. That}
R/W ^{is, the most significant sign bit is copied to the bits that}
become short by the right shift for refill. Select a value
between 0 and 10 for the right-shift amount of error
amount. If a value outside the range is set, the setting is
invalid and the operation is not guaranteed.
Right-shift amount
Right-shift amount
0000: 0
1000: 8
0001: 1
1001: 9
0010: 2
1010: 10
0011: 3
1011: 11 (invalid)
0100: 4
1100: 12 (invalid)
0101: 5
1101: 13 (invalid)
0110: 6
1110: 14 (invalid)
0111: 7
1111: 15 (invalid)
11
LKCYC3 0
10
LKCYC2 0
9
LKCYC1 0
8
LKCYC0 0
R/W These bits set a PLL lock threshold value. For PLL lock
R/W ^{threshold values, see table 15.3.13. Set an LKCYC value}
that is not larger than PWMCYC (LKCYC =< PWMCYC). If
R/W _{a value larger than PWMCYC is set, the operation is not}
R/W ^guaranteed.
7
ULREF3 0
6
ULREF2 0
5
ULREF1 0
4
ULREF0 0
R/W These bits specify a reference value for the number of
R/W ^{continuous LKZF = 1 states (outside the threshold value}
range) when PLL is locked (LKF = 1). This value is
R/W _{compared with the ULCNT value. When ULCNT >=}
R/W ^{ULREF, the LKF bit in STSTR is set to 0.}
3
LKREF3 0
2
LKREF2 0
1
LKREF1 0
0
LKREF0 0
R/W These bits specify a reference value for the number of
R/W ^{continuous LKZF = 0 states (within the threshold value}
range) when PLL is unlocked (LKF = 0). This value is
R/W _{compared with the LKCNT value. When LKCNT >=}
R/W ^{LKREF, the LKF bit in STSTR is set to 1.}
Rev. 1.00 Nov. 14, 2007 Page 568 of 1262
REJ09B0437-0100