SH7670 Datasheet, PDF (693/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
8
BRDYE
0
R/W Buffer Ready Interrupts Enable
Enables or disables the USB interrupt output when
the BRDY interrupt is detected.
0: Interrupt output disabled
1: Interrupt output enabled
7 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Note: * The RSME, DVSE, and CTRE bits can be set to 1 only when the function controller
function is selected; do not set these bits to 1 to enable the corresponding interrupt
output when the host controller function is selected.
17.3.11 Interrupt Enable Register 1 (INTENB1)
INTENB1 is a register that specifies the various interrupt masks when the host controller function
is selected. On detecting the interrupt corresponding to the bit in this register to which software
has set 1, this module generates the USB interrupt.
This module sets 1 to each status bit in INTSTS1 when a detection condition of the corresponding
interrupt source has been satisfied regardless of the set value in INTENB1 (regardless of whether
the interrupt output is enabled or disabled).
While the status bit in INTSTS1 corresponding to the interrupt source indicates 1, this module
generates the USB interrupt when software modifies the corresponding interrupt enable bit in
INTENB1 from 0 to 1.
When the function controller function is selected, the interrupts should not be enabled.This
register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
BCHGE
—
DTCHE
ATT
CHE
—
—
—
—
EOF
ERRE
SIGNE SACKE
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R/W R R/W R/W R
R
R
R R/W R/W R/W R
R
R
R
Rev. 1.00 Nov. 14, 2007 Page 667 of 1262
REJ09B0437-0100