SH7670 Datasheet, PDF (241/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 7 Bus State Controller (BSC)
7.4.11 Internal Bus Master Bus Priority Register (IBMPR)
IBMPR is a 32-bit register that sets the bus priority for the internal bus masters excluding the
CPU.
If internal bus masters excluding the same CPU are set at different priority levels, the highest one
will be effective. After an attempt to set internal bus masters in an overlapping manner, if some of
them failed to be set, then these failing bus masters will not be able to acquire bus mastership.
Rewriting this register while any of the A-DMAC (including F-DMAC), E-DMAC, and DMAC is
operating is prohibited. When rewriting this register, make sure that none of the A-DMAC
(including F-DMAC), E-DMAC, and DMAC is not started.
For details, see section 7.5.9 (2), Access from the Side of the LSI Internal Bus Master.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16


0P1R[1:0]


0P2R[1:0]


0P3R[1:0]




Initial Value 0
0
0
1
0
0
1
0
0
0
1
1
0
0
0
0
R/W: R
R R/W R/W R
R R/W R/W R
R R/W R/W R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
















Initial Value 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
31, 30
Bit Name

Initial
Value
All 0
29, 28 0P1R[1:0] 01
R/W Description
R Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Of the internal bus masters excluding the CPU (that is,
A-DMAC (including F-DMAC), E-DMAC, and DMAC),
set the internal bus master having the highest priority
level.
00: No setting
01: A-DMAC (including F-DMAC)
10: E-DMAC
11: DMAC
Rev. 1.00 Nov. 14, 2007 Page 215 of 1262
REJ09B0437-0100