SH7670 Datasheet, PDF (679/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
31 to 0 FIFOPORT All 0
[31:0]
R/W FIFO Port
Accessing these bits allow reading the received data
from the FIFO buffer or writing the transmit data to
the FIFO buffer.
These bits can be accessed only while the FRDY bit
in each control register (CFIFOCTR, D0FIFOCTR, or
D1FIFOCTR) is 1.
The valid bits in this register depend on the settings
of the MBW bits (access bit width setting) and
BIGEND bit (endian setting) as shown in tables 17.8
to 17.10.
Table 17.8 Endian Operation in 32-Bit Access (when MBW = 10)
BIGEND Bit
0
1
Bits 31 to 24
N + 3 address
N + 0 address
Bits 23 to 16
N + 2 address
N + 1 address
Bits 15 to 8
N + 1 address
N + 2 address
Bits 7 to 0
N + 0 address
N + 3 address
Table 17.9 Endian Operation in 16-Bit Access (when MBW = 01)
BIGEND Bit
Bits 31 to 24
Bits 23 to 16
Bits 15 to 8
Bits 7 to 0
0
Writing: invalid, reading: prohibited* N + 1 address
N + 0 address
1
N + 0 address N + 1 address
Writing: invalid, reading: prohibited*
Note: * Reading data from the invalid bits in a word or byte unit is prohibited.
Table 17.10 Endian Operation in 8-Bit Access (when MBW = 00)
BIGEND Bit
Bits 31 to 24
Bits 23 to 16
Bits 15 to 8
Bits 7 to 0
0
Writing: invalid, reading: prohibited*
N + 0 address
1
N + 0 address
Writing: invalid, reading: prohibited*
Note: * Reading data from the invalid bits in a word or byte unit is prohibited.
Rev. 1.00 Nov. 14, 2007 Page 653 of 1262
REJ09B0437-0100