SH7670 Datasheet, PDF (564/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
Checksum descriptor
C[i]CSM[1:0] = H'3
C[i]CM[6:0] = H'7f
C[i]HM[4:0] = H'1f
C[i]F2
=1
C[i]F0
=1
Checksum descriptor
C[i]CSM[1:0] = H'3
C[i]CM[6:0] = H'7f
C[i]HM[4:0] = H'1f
C[i]F2
=1
C[i]F0
=1
Checksum descriptor
C[i]CSM[1:0] = H'2
C[i]CM[6:0] = H'7f
C[i]HM[4:0] = H'1f
C[i]F2
=0
C[i]F0
=1
Checksum descriptor
C[i]CSM[1:0] = H'0
C[i]CM[6:0] = H'7f
C[i]HM[4:0] = H'1f
C[i]F2
=0
C[i]F0
=1
Invalid descriptor
C[i]CSM[1:0] = ANY
C[i]CM[6:0] = ANY
C[i]HM[4:0] = ANY
C[i]F2
= ANY
C[i]F0
=0
Checksum descriptor
C[i]CSM[1:0] = H'1
C[i]CM[6:0] = H'7f
C[i]HM[4:0] = H'1f
C[i]F2
=1
C[i]F0
=1
Invalid descriptor
C[i]CSM[1:0] = ANY
C[i]CM[6:0] = ANY
C[i]HM[4:0] = ANY
C[i]F2
= ANY
C[i]F0
=0
(a) Example of continuously allocating
checksum descriptors each of which
completes one processing
(b) Example of splitting processing into
several checksum descriptors and
allocating the last checksum descriptor
that completes processing
Figure 14.3 Examples of Allocating Checksum Descriptors
Rev. 1.00 Nov. 14, 2007 Page 538 of 1262
REJ09B0437-0100