SH7670 Datasheet, PDF (545/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
Bit
12
11 to 9
8
7 to 5
4
3 to 1
Initial
Bit Name Value R/W Description
FECC_LIE 0
R/W "Last Descriptor Processing End" Notification Interrupt Request
Enable
Specifies whether to enable or disable the "last descriptor
processing end" interrupt request when processing of the last
descriptor ends (FECI_LI mask).
0: Disables the "last descriptor processing end" interrupt
request.
1: Enables the "last descriptor processing end" interrupt
request.
—
All 0 R Reserved
These bits are always read as 0. The write value should always
be 0.
FECC_NIE 0
R/W "Invalid Descriptor" Notification Interrupt Request Enable
Specifies whether to enable or disable the "invalid descriptor"
notification interrupt request when the invalid descriptor is
fetched (FECI_NI mask).
0: Disables the "invalid descriptor" notification interrupt request.
1: Enables the "invalid descriptor" notification interrupt request.
—
All 0 R Reserved
These bits are always read as 0. The write value should always
be 0.
FECC_EIE 0
R/W "Processing End" Interrupt Request Enable
Specifies whether to enable or disable the "processing end"
interrupt request when processing ends (FECI_EI mask).
0: Disables the "processing end" interrupt request.
1: Enables the "processing end" interrupt request.
—
All 0 R Reserved
These bits are always read as 0. The write value should always
be 0.
Rev. 1.00 Nov. 14, 2007 Page 519 of 1262
REJ09B0437-0100