SH7670 Datasheet, PDF (906/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 20 Host Interface (HIF)
20.4.1 HIF Index Register (HIFIDX)
HIFIDX is a 32-bit register used to specify the register read from or written to by an external
device when the HIFRS pin is held low. HIFIDX can be only read by the on-chip CPU. HIFIDX
can be only written to by an external device while the HIFRS pin is driven high.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0







 REG5 REG4 REG3 REG2 REG1 REG0 BYTE1 BYTE0
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit Bit Name Value
31 to 8 
All 0
7
REG5
0
6
REG4
0
5
REG3
0
4
REG2
0
3
REG1
0
2
REG0
0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
HIF Internal Register Select
These bits specify which register among HIFGSR,
HIFSCR, HIFMCR, HIFIICR, HIFEICR, HIFADR,
HIFDATA, and HIFBCR is accessed by an external
device.
000000: HIFGSR
000001: HIFSCR
000010: HIFMCR
000011: HIFIICR
000100: HIFEICR
000101: HIFADR
000110: HIFDATA
001111: HIFBCR
Other than above: Setting prohibited
Rev. 1.00 Nov. 14, 2007 Page 880 of 1262
REJ09B0437-0100