SH7670 Datasheet, PDF (78/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 2 CPU
Operation
Classification Types Code
Function
System
control
14
CLRT
T bit clear
CLRMAC MAC register clear
LDBANK Register restoration from specified register
bank entry
LDC
Load to control register
LDS
Load to system register
NOP
No operation
RESBANK Register restoration from register bank
RTE
Return from exception handling
SETT
T bit set
SLEEP Transition to power-down mode
STBANK Register save to specified register bank entry
STC
Store control register data
STS
Store system register data
TRAPA Trap exception handling
Floating-point 19
instructions
FABS
FADD
Floating-point absolute value
Floating-point addition
FCMP
Floating-point comparison
FCNVDS Conversion from double-precision to single-
precision
FCNVSD Conversion from single-precision to double -
precision
FDIV
Floating-point division
FLDI0
Floating-point load immediate 0
FLDI1
Floating-point load immediate 1
FLDS
Floating-point load into system register FPUL
FLOAT Conversion from integer to floating-point
FMAC
Floating-point multiply and accumulate
operation
FMOV
Floating-point data transfer
FMUL
Floating-point multiplication
FNEG
Floating-point sign inversion
No. of
Instructions
36
48
Rev. 1.00 Nov. 14, 2007 Page 52 of 1262
REJ09B0437-0100