SH7670 Datasheet, PDF (1269/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 29 Electrical Characteristics
29.4.19 STIF Module Signal Timing (5)
(With Stream Output Set Synchronized with STn_CLKOUT Rise Time)
Table 29.25 STIF Module Signal Timing (5)
Conditions:
V_CC = V_CC (PLL) = DV12 = UV12 = 1.1 to 1.3 V, V_CCQ = DV33 = 3.1 to 3.5 V,
AV12 = 1.1 to 1.3 V, AV33 = 3.1 to 3.5 V,
V_SS = V_SS (PLL) = DG12 = UG12 = V_SSQ = DG33 = AG12 = AG33 = 0 V,
Ta = –20 to 70°C (regular specifications),
–40 to 85°C (wide temperature specifications)
Item
STn_SYC output delay time 5
STn_VLD output delay time 5
STn_Dm output delay time 5
STn_REQ input setup time 5
STn_REQ input hold time 5
Symbol
t
STSD5
t_STVD5
t_STDD5
t
STRS5
t
STRH5
Min.



9.5
9.5
Max.
Unit
5
ns
5
ns
5
ns

ns

ns
Figure
29.72
ST_CLKOUT output
STn_SYC output
STn_VLD output
STn_D7 - STn_D0 output
STn_REQ input
t_STSD6
t_STVD6
t_STDD6
t_STRS6
t_STRH6
t_STSD6
t_STVD6
t_STDD6
t_STRS6
t_STRH6
Figure 29.72 STIF Module Signal Timing (5)
Rev. 1.00 Nov. 14, 2007 Page 1243 of 1262
REJ09B0437-0100