SH7670 Datasheet, PDF (18/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

14.4 Channel Operation ............................................................................................................ 535
14.4.1 Descriptor Format............................................................................................. 535
14.4.2 Basic Channel Operation .................................................................................. 536
14.4.3 Checksum ......................................................................................................... 537
14.5 FEC Channel Operation.................................................................................................... 539
14.5.1 Descriptor Format for FEC Channel................................................................. 539
14.5.2 Basic FEC Channel Operation .......................................................................... 540
Section 15 Stream Interface (STIF).................................................................. 543
15.1 Features............................................................................................................................. 543
15.2 Input/Output Pins.............................................................................................................. 545
15.3 Register Descriptions........................................................................................................ 546
15.3.1 STIF Mode Select Register (STMDR).............................................................. 547
15.3.2 STIF Control Register (STCTLR) .................................................................... 550
15.3.3 STIF Internal Counter Control Register (STCNTCR) ...................................... 552
15.3.4 STIF Internal Counter Set Register (STCNTVR)............................................. 553
15.3.5 STIF Status Register (STSTR).......................................................................... 553
15.3.6 STIF Interrupt Enable Register (STIER) .......................................................... 556
15.3.7 STIF Transfer Size Register (STSIZER) (n = 0,1) ........................................... 557
15.3.8 STIFPWM Mode Register (STPWMMR) ........................................................ 558
15.3.9 STIFPWM Control Register (STPWMCR) ...................................................... 562
15.3.10 STIFPWM Register (STPWMR)...................................................................... 564
15.3.11 STIFPCR0, STIFPCR01 Registers (STPCR0R, STPCR1R) ............................ 565
15.3.12 STIFSTC0, STIFSTC1 Registers (STSTC0R, STSTC1R)............................... 566
15.3.13 STIF Lock Control Register (STLKCR)........................................................... 567
15.3.14 STIF Debugging Status Register (STDBGR) ................................................... 570
15.4 Examples of Clock Connection to Another Device .......................................................... 570
15.4.1 A Basic Example .............................................................................................. 570
15.4.2 An Example of Clock Connection
When Another Device Has No Clock Input...................................................... 570
15.4.3 An Example of Clock Connection
When Another Device Has No Clock Output ................................................... 571
15.5 Input/Output Timing......................................................................................................... 571
15.6 PCR Clock Recovery Module (PCRRCV) ....................................................................... 578
15.6.1 Operation of PCR Clock Recovery................................................................... 579
15.6.2 PCR Clock Recovery Operation ....................................................................... 581
Rev. 1.00 Nov. 14, 2007 Page xviii of xxvi