SH7670 Datasheet, PDF (512/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Multi-Buffer Frame Receive Processing
If an error occurs during multi-buffer frame reception, the processing shown in figure 13.7 is
carried out by the E-DMAC.
Where the receive descriptor is shown as inactive (RACT bit = 0) in the figure, buffer data has
already been received normally, and where the receive descriptor is shown as active (RACT bit =
1), this indicates a buffer for which reception has not yet been performed. If a frame receive error
occurs in the first descriptor part where the RACT bit = 1 in the figure, reception is halted
immediately and a status write-back to the descriptor is performed.
If error interrupts are enabled in the EtherC/E-DMAC status interrupt permission register
(EESIPR), an interrupt is generated immediately after the write-back. If there is a new frame
receive request, reception is continued from the buffer after that in which the error occurred.
Descriptors
RR
AD
CL
TE
RR
FF
PP
10
00 10
00 00
00
Inactivates RACT and writes RFE, RFS
E-DMAC _{Descriptor read}
10
Write-back
10
00
01
00
10 00
10 00
10 00
11 00
Start of frame
Receive error
occurrence
New frame reception
continues from buffer
Buffer
Figure 13.7 E-DMAC Operation after Receive Error
Received data
Unreceived data
Rev. 1.00 Nov. 14, 2007 Page 486 of 1262
REJ09B0437-0100