SH7670 Datasheet, PDF (946/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 21 Compare Match Timer (CMT)
21.5 Usage Notes
21.5.1 Conflict between Write and Compare-Match Processes of CMCNT
When the compare match signal is generated in the T2 cycle while writing to CMCNT, clearing
CMCNT has priority over writing to it. In this case, CMCNT is not written to. Figure 21.5 shows
the timing to clear the CMCNT counter.
Peripheral clock
(Pφ)
Address signal
Internal write signal
Counter clear signal
CMCSR write cycle
T1
T2
CMCNT
CMCNT
N
H'0000
Figure 21.5 Conflict between Write and Compare Match Processes of CMCNT
Rev. 1.00 Nov. 14, 2007 Page 920 of 1262
REJ09B0437-0100