SH7670 Datasheet, PDF (347/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 8 Direct Memory Access Controller (DMAC)
8.4 Operation
When there is a DMA transfer request, the DMAC starts the transfer according to the
predetermined channel priority order; when the transfer end conditions are satisfied, it ends the
transfer. Transfers can be requested in three modes: auto request, external request, and on-chip
peripheral module request. In bus mode, the burst mode or the cycle steal mode can be selected.
8.4.1 Transfer Flow
After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA
transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation
register (DMAOR), three reload registers (RSAR, RDAR, and RDMATCR), and DMA extension
resource selector (DMARS) are set for the target transfer conditions, the DMAC transfers data
according to the following procedure:
1. Checks to see if transfer is enabled (DE = 1, DME = 1, TEMASK = 0 and TE = 0 [or
TEMASK = 1], AE = 0, NMIF = 0)
2. When a transfer request comes and transfer is enabled, the DMAC transfers one transfer unit of
data (depending on the TS[1:0] settings). For an auto request, the transfer begins automatically
when the DE bit and DME bit are set to 1. The DMATCR value will be decremented by 1 for
each transfer. The actual transfer flows vary by address mode and bus mode.
3. When half of the specified transfer count is exceeded (when DMATCR reaches half of the
initial value), an HEI interrupt is sent to the CPU if the HIE bit in CHCR is set to 1.
4. When TEMASK = 0, if transfer has been completed for the specified count (that is, DMATCR
reaches 0), the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI
interrupt is sent to the CPU. When TEMASK = 1, if DMATCR reaches 0, TE is set to 1. The
specified RSAR, RDAR, and RDMATC values are reloaded into RSAR, RDAR, and
RDMATC, and the transfer operation continues until there are no more transfer requests.
5. When an address error in the DMAC or an NMI interrupt is generated, the transfer is
terminated. Transfers are also terminated when the DE bit in CHCR or the DME bit in
DMAOR is cleared to 0.
Figure 8.2 is a flowchart of this procedure.
Rev. 1.00 Nov. 14, 2007 Page 321 of 1262
REJ09B0437-0100