SH7670 Datasheet, PDF (537/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
Initial
Bit
Bit Name Value R/W
19
C[i]DA
0
R/W
18
C[i]SA
0
R/W
17, 16 C[i]CSM[1:0] 00
R/W
15 to 3 —
All 0 R/W
Description
Destination Attribute
Specifies whether the data read source uses the
channel [i] (the destination address is not used) of the
STIF or the destination address (memory such as
SDRAM).
0: Uses the destination address (memory such as
SDRAM).
1: Uses the channel [i] of the STIF
Source Attribute
Specifies whether the data read source uses the
channel [i] (the source address is not used) of the STIF
or the source address (memory such as SDRAM).
0: Uses the source address (memory such as SDRAM).
1: Uses the channel [i] of the STIF
Checksum Mode
00: Checksum (not initialized, not written back)
Not beginning of data
Not end of data
01: Checksum (not initialized, written back)
Not beginning of data
End of data
10: Checksum (initialized, not written back)
Beginning of data
Not end of data
11: Checksum (initialized, written back)
Beginning of data
End of data
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 14, 2007 Page 511 of 1262
REJ09B0437-0100