SH7670 Datasheet, PDF (1219/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 29 Electrical Characteristics
Th
T1
Twx
T2
Tf
CKIO
t_AD1
t_AD1
A25 to A0
t_CSD1
t_CSD1
CSn
t_WED2
t_WED2
WEn
RD/WR
Read
RD
D31 to D0
t_RSD
t_RWD1
t_RWD1
t_RSD
t_RDS1
t_RDH1
t_RWD1
t_RWD1
RD/WR
Write
D31 to D0
BS
DACKn
TENDn*
t_WDD1
t_BSD
t_DACD
t_BSD
t_WTH
t_WTH
t_WDH1
t_DACD
WAIT
t_WTS
t_WTS
Note: * The waveforms for DACKn and TENDn are produced when the active low state is specified.
Figure 29.15 SRAM Bus Cycle with Byte Selection (SW = One Cycle, HW = One Cycle,
One Asynchronous External Wait Cycle, BAS = 1 (Write Cycle WE Control))
Rev. 1.00 Nov. 14, 2007 Page 1193 of 1262
REJ09B0437-0100