SH7670 Datasheet, PDF (30/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 1 Overview
Classification
CPU
Interrupts
(sources)
Module/Function Description
Floating-point unit •
(FPU)
•
Floating-point co-processor included
Supports single-precision (32-bit) and double-precision
(64-bit)
• Supports data type and exceptions that conform to
IEEE754 standard
• Two rounding modes: Round to nearest and round to zero
• Denormalization modes: Flush to zero
• Floating-point registers
• Sixteen 32-bit floating-point registers (single-precision ×
16 words or double-precision × 8 words)
• Two 32-bit floating-point system registers
• Supports FMAC (multiplication and accumulation)
instructions
• Supports FDIV (division) and FSQRT (square root)
instructions
• Supports FLDI0/FLDI1 (load constant 0/1) instructions
• Instruction execution time
Latency (FMAC/FADD/FSUB/FMUL): Three cycles
(single-precision), eight cycles (double-precision)
Pitch (FMAC/FADD/FSUB/FMUL): One cycle (single-
precision), six cycles (double-precision)
Note: FMAC only supports single-precision.
• Five-stage pipeline
Interrupt controller •
(INTC)
•
Nine external interrupt pins (NMI and IRQ7 to IRQ0)
On-chip peripheral interrupts: Priority level set for each
module
• Sixteen priority levels available
• Register bank enabling fast register saving and restoring
in interrupt handling
Rev. 1.00 Nov. 14, 2007 Page 4 of 1262
REJ09B0437-0100