SH7670 Datasheet, PDF (915/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 20 Host Interface (HIF)
20.4.6 HIF External Interrupt Control Register (HIFEICR)
HIFEICR is a 32-bit register used to issue interrupts to an external device connected to the HIF
from this LSI. Access to HIFEICR by an external device should be performed with HIFEICR
specified by bits REG5 to REG0 in HIFIDX and the HIFRS pin low.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0







 EIC6 EIC5 EIC4 EIC3 EIC2 EIC1 EIC0 EIR
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit Bit Name Value R/W Description
31 to 8 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
7
EIC6
0
R/W External Interrupt Source
6
EIC5
0
5
EIC4
0
4
EIC3
0
3
EIC2
0
2
EIC1
0
R/W These bits specify the source for interrupts generated by
R/W ^{the EIR bit. These bits can be written to from both an}
external device and the on-chip CPU. By using these bits,
R/W _{fast execution of interrupt exception handling is possible.}
R/W ^{These bits are completely under software control, and}
R/W ^{their values have no effect on the operation of this LSI.}
1
EIC0
0
R/W
0
EIR
0
R/W External Interrupt Request
While this bit is 1, the HIFINT pin is asserted to issue an
interrupt request to an external device from this LSI.
Rev. 1.00 Nov. 14, 2007 Page 889 of 1262
REJ09B0437-0100