SH7670 Datasheet, PDF (465/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 13 Ethernet Controller Direct Memory Access Controller (E-DMAC)
13.2.1 E-DMAC Mode Register (EDMR)
EDMR is a 32-bit readable/writable register that specifies the operating mode of the E-DMAC.
The settings in this register are normally made in the initialization process following a reset. If the
EtherC and E-DMAC are initialized by means of this register during data transmission, abnormal
data may be sent onto the line. Operating mode settings must not be changed while the transmit
and receive functions are enabled. To change the operating mode, the EtherC and E-DMAC
modules are got into at their initial state by means of the software reset bit (SWR) in this register,
then make new settings. It takes 64 cycles of the internal bus clock Bφ to initialize the EtherC and
E-DMAC. Therefore, registers of the EtherC and E-DMAC should be accessed after 64 cycles of
the internal bus clock Bφ has elapsed.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0









DE DL1 DL0 

 SWR
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R R/W R/W R/W R
R
R R/W
Initial
Bit
Bit Name value R/W Description
31 to 7 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
6
DE
0
R/W E-DMAC Data Endian Convert
Selects whether or not the endian format is converted
on data transfer by the E-DMAC. However, the endian
format of the descriptors and E-DMAC register values
are not converted regardless of this bit setting.
0: Endian format not converted (big endian)
1: Endian format converted (little endian)
Rev. 1.00 Nov. 14, 2007 Page 439 of 1262
REJ09B0437-0100