SH7670 Datasheet, PDF (1283/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

H
HIF Module Signal Timing .................. 1230
High-performance user debugging
interface (H-UDI) ................................. 1083
Host interface (HIF)................................ 875
H-UDI commands................................. 1086
H-UDI interrupt ............................ 143, 1090
H-UDI reset .......................................... 1090
H-UDI-Related Pin Timing .................. 1237
I
I/O Port Timing .................................... 1229
I/O ports................................................ 1039
I²C bus format......................................... 851
I²C bus interface 3 (IIC3) ....................... 833
IIC3 Module Timing............................. 1220
Immediate data ......................................... 38
Immediate data accessing ......................... 38
Immediate data format.............................. 35
Initial values of control registers .............. 33
Initial values of general registers .............. 33
Initial values of system registers............... 33
Instruction features ................................... 36
Instruction format ..................................... 45
Instruction set ........................................... 49
Integer division instructions ................... 125
Interrupt controller (INTC)..................... 131
Interrupt exception handling................... 122
Interrupt exception
handling vectors and priorities................ 147
Interrupt priority level............................. 121
Interrupt response time ........................... 155
IRQ interrupts ......................................... 144
J
Jump table base register (TBR) ................ 31
L
Load-store architecture ............................. 36
Logic operation instructions...................... 62
Low-power SDRAM............................... 269
LRU .......................................................... 89
M
Magic packet detection ........................... 433
Manual reset............................................ 116
Master receive operation......................... 854
Master transmit operation ....................... 852
Memory-mapped cache........................... 102
MII frame timing..................................... 428
Module standby function ........................ 393
Multi-buffer frame transmit
/receive processing.................................. 485
multiplexed pin ....................................... 987
Multiply and accumulate register
high (MACH)............................................ 32
Multiply and accumulate register
low (MACL) ............................................. 32
Multiply/Multiply-and-accumulate
operations.................................................. 37
N
NMI interrupt.......................................... 143
Noise filter .............................................. 864
Non-compressed modes .......................... 603
Non-numbers (NaN) ................................. 79
Normal space interface ........................... 224
Note on inputting external clock ............. 359
Note on resonator.................................... 360
Note on using a PLL
oscillation circuit..................................... 360
Note on using an external
crystal resonator ...................................... 359
Rev. 1.00 Nov. 14, 2007 Page 1257 of 1262
REJ09B0437-0100