SH7670 Datasheet, PDF (577/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 15 Stream Interface (STIF)
Bit
8
7
6 to 3
2
1
0
Initial
Bit Name Value R/W Description
RCV
0
R/W Enables the recovery functions when outputting packets in
TS mode 1 or TS mode 2.
0: Recovery functions disabled
1: Recovery functions enabled
TRICK 0
R/W Enables the function that transfers stream independently of
timestamp when outputting packets in TS mode 1 or TS
mode 2.
0: Transfer function disabled
1: Transfer function enabled

All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
REQEN 0
R/W Enables or disables DMA transfer requests to the A-DMAC.
0: Disabled
1: Enabled
EN
0
R/W Enables or disables stream input/output.
0: Disabled
1: Enabled
SRST
0
R/W Setting this bit to 1 causes the internal state of this LSI to be
initialized with register settings retained.
When a TS packet is received for the first time after the
initialization, the timestamp value of the TS packet is
reloaded to the internal counter for timestamp.
While 1 is read from this bit, the initialization is in progress.
This bit is automatically cleared to 0.
Whenever the STMDR setting is modified, be sure to set
SRST to 1 to initialize this LSI and then set EN and REQEN
to 1 to enable stream transfer.
Rev. 1.00 Nov. 14, 2007 Page 551 of 1262
REJ09B0437-0100