SH7670 Datasheet, PDF (42/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 1 Overview
Classification Symbol
Bus control DQMUL
DQMLU
DQMLL
CE1A
CE1B
CE2A
CE2B
ICIOWR
ICIORD
WE
IOIS16
Direct memory DREQ0, DREQ1
access
controller
(DMAC)
DACK0, DACK1
Ethernet
controller
(EtherC)
TEND0, TEND1
CRS
COL
MII_TXD3 to
MII_TXD0
TX_EN
I/O Name
Function
O Second byte
select
Selects data bus bits 23 to 16 of
SDRAM.
O Third byte select Selects data bus bits 15 to 8 of
SDRAM.
O Least significant Selects data bus bits 7 to 0 of
byte select
SDRAM.
O PCMCIA card
select (lower)
Chip enable signal pin for PCMCIA
connected to area 5
O PCMCIA card
select (lower)
Chip enable signal pin for PCMCIA
connected to area 6
O PCMCIA card
select (upper)
Chip enable signal pin for PCMCIA
connected to area 5
O PCMCIA card
select (upper)
Chip enable signal pin for PCMCIA
connected to area 6
O PCMCIA I/O write Pin connected to the PCMCIA I/O
strobe
write strobe
O PCMCIA I/O read Pin connected to the PCMCIA I/O
strobe
read strobe
O PCMCIA memory Pin connected to the PCMCIA
write strobe
memory write strobe
I PCMCIA dynamic Indicates the 16-bit I/O of PCMCIA in
bus sizing
little-endian mode. Fix this pin low in
big-endian mode.
I DMA-transfer
request
Input pins to receive external requests
for DMA transfer
O DMA-transfer
request
acknowledge
Output pins for signals indicating
acknowledge of external requests
from external devices
O DMA-transfer end Output pins for DMA transfer end
output
I Carrier sense Carrier sensing pin
I Collision
Collision detecting pin
O Transmit data 4-bit transmit data pins
O Transmit enable Indicates that transmit data is ready
on the MII_TXD3 to MII_TXD0 pins.
Rev. 1.00 Nov. 14, 2007 Page 16 of 1262
REJ09B0437-0100