SH7670 Datasheet, PDF (608/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 15 Stream Interface (STIF)
PWMUEN to 1 disables the PWM control variable outside the acceptable comparison
result range specified by the PWMCYC bits to be reflected in the PWM control output.
This function can prevent an abnormal PCR (caused by PCR error due to transmission error
or protocol violation at the transmitter side) from being reflected in clock recovery. For
measures against abnormal PCRs, see the procedure examples 1 and 2 described later.
G. The PWMOUT waveform with a reflected PWM control variable is output from the
PWMOUT pin as shown in figure 15.9.
H. The internal STC and PCR register values are compared each time a PCR_PID packet
arrives. By configuring a feedback circuit including an external low-pass filter (LPF) and
an external VCXO, which makes the comparison (STC value - PCR value) result to be 0,
the VCXO clock frequency is adjusted.
• Example 2: Clock recovery using the PCRRCV and software
A. Set PWMSEL to 1 to disable the clock recovery using the PCRRCV hardware. Also set
PCRE to 1 to enable interrupt requests made by each PCR arrival pulse.
B. The PCRRCV settings and transfers of the PCRRCV internal registers are the same as
those described in steps 2 to 5of Example 1. Notes 1 to 4 for table 15.5 apply to the case of
the first arrival of PCR after the PCR continuity is lost. Since the STC counter that has no
continuity with the arrived internal PCR register is transferred to the internal STC register,
it is not appropriate to calculate the difference (STC value - PCR value) by the CPU.
C. Confirm that transfer between the PCRRCV internal registers has been completed (PCRF =
1), and then set PCRF to 0. After that, set the STCRS and PCRRS bits to 1 to enable
transfer from the STC register to STSTC0R and STSTC1R, as well as transfer from the
PCR register to STSTC0R and STSTC1R. Then read STSTC0R/STSTC1R and
STPCR0R/STPCR1R. Furthermore, to obtain the STC counter value for setting to the
MPEG2 decoder, set the STCXP bit to 1 to enable transfer from the STC counter to
STSTC0R and STSTC1R. Then read STSTC0R and STSTC1R.
D. A PCRF read value of 0 means that no PCR_PID packet arrived during the register read
stage in step 3. This shows that the reading of STSTC0R/STSTC1R and
STPCR0R/STPCR1R in step 3 was successful. On the other hand, a PCRF read value of 1
shows an arrival of PCR_PID packet during the register read stage in step 3. It is not
certain that the read STSTC0R/STSTC1R and STPCR0R/STPCR1R are the values of the
internal STC and PCR registers that arrived previously or those that arrived during the
register read stage. Therefore, go back to step 3 and repeat the procedure.
Rev. 1.00 Nov. 14, 2007 Page 582 of 1262
REJ09B0437-0100