SH7670 Datasheet, PDF (806/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
(c) During no-data control transfers
 At the status stage, an OUT or PING token is received
At the control write transfer stage, if the number of receive data exceeds the wLength value of the
USB request, it cannot be recognized as a control transfer sequence error. At the control read
transfer status stage, packets other than zero-length packets are received by an ACK response and
the transfer ends normally.
When a CTRT interrupt occurs in response to a sequence error (SERR = 1), the CTSQ = 110 value
is retained until CTRT = 0 is written from the system (the interrupt status is cleared). Therefore,
while CTSQ = 110 is being held, the CTRT interrupt that ends the setup stage will not be
generated even if a new USB request is received. (This module retains the setup stage end, and
after the interrupt status has been cleared by software, a setup stage end interrupt is generated.)
Setup
token reception
CTSQ = 000
setup stage
Setup token reception
CTSQ = 110
control transfer
sequence error
5
Error
detection
Setup token reception
Error detection and IN token reception
are valid at all stages in the box.
ACK
trans-
mission
CTSQ = 001
1 control read
data stage
OUT token
2
CTSQ = 010
control read
status stage
ACK
trans-
mission
4
CTSQ = 000
idle stage
4
ACK
transmission
1
CTSQ = 011
control write
data stage
IN token
3
CTSQ = 100
control write
status stage
ACK
reception
ACK
transmission
Note:
CTRT interrupts
(1) Setup stage completed
(2) Control read transfer status stage transition
(3) Control write transfer status stage transition
(4) Control transfer completed
(5) Control transfer sequence error
CTSQ = 101
1
control write
no data
status stage
ACK
reception
Figure 17.7 Control Transfer Stage Transitions
Rev. 1.00 Nov. 14, 2007 Page 780 of 1262
REJ09B0437-0100