SH7670 Datasheet, PDF (86/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 2 CPU
Instruction
CLIPS.B Rn
CLIPS.W Rn
CLIPU.B Rn
CLIPU.W Rn
DIV1
Rm,Rn
DIV0S Rm,Rn
DIV0U
DIVS
R0,Rn
DIVU
R0,Rn
DMULS.L Rm,Rn
DMULU.L Rm,Rn
DT
Rn
EXTS.B Rm,Rn
EXTS.W Rm,Rn
Instruction Code
Operation
Execu-
tion
Cycles
T Bit
Compatibility
SH2,
SH2E SH4 SH-2A
0100nnnn10010001 When Rn > (H'0000007F),
1

Yes
(H'0000007F) → Rn, 1 → CS
when Rn < (H'FFFFFF80),
(H'FFFFFF80) → Rn, 1 → CS
0100nnnn10010101 When Rn > (H'00007FFF), 1

Yes
(H'00007FFF) → Rn, 1 → CS
When Rn < (H'FFFF8000),
(H'FFFF8000) → Rn, 1 → CS
0100nnnn10000001 When Rn > (H'000000FF), 1

Yes
(H'000000FF) → Rn, 1 → CS
0100nnnn10000101 When Rn > (H'0000FFFF), 1

Yes
(H'0000FFFF) → Rn, 1 → CS
0011nnnnmmmm0100 1-step division (Rn ÷ Rm)
1
Calcu-
lation
result
Yes Yes Yes
0010nnnnmmmm0111 MSB of Rn → Q,
1
MSB of Rm → M, M ^ Q → T
Calcu-
lation
result
Yes Yes Yes
0000000000011001 0 → M/Q/T
1
0
Yes Yes Yes
0100nnnn10010100 Signed operation of Rn ÷ R0 36

Yes
→ Rn 32 ÷ 32 → 32 bits
0100nnnn10000100 Unsigned operation of Rn ÷ R0 34

Yes
→ Rn 32 ÷ 32 → 32 bits
0011nnnnmmmm1101 Signed operation of Rn × Rm 2
→ MACH, MACL
32 × 32 → 64 bits

Yes Yes Yes
0011nnnnmmmm0101 Unsigned operation of Rn × 2
Rm → MACH, MACL
32 × 32 → 64 bits
0100nnnn00010000 Rn – 1 → Rn
1
When Rn is 0, 1 → T
When Rn is not 0, 0 → T

Yes Yes Yes
Compa- Yes Yes Yes
rison
result
0110nnnnmmmm1110 Byte in Rm is
sign-extended → Rn
1

Yes Yes Yes
0110nnnnmmmm1111 Word in Rm is
sign-extended → Rn
1

Yes Yes Yes
Rev. 1.00 Nov. 14, 2007 Page 60 of 1262
REJ09B0437-0100