SH7670 Datasheet, PDF (550/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
14.2.14 FEC DMAC Processing Descriptor Current Address Register (FECDCA)
Do not write any value to this register when FECC_E is set to 1.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FECDCA[31:16]
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
FECDCA[15:4]
FECDCA[3:0]
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
R
R
R
Bit
31 to 4
3 to 0
Bit Name
Initial
Value R/W
FECDSA[31:4] All 0 R/W
FECDSA[3:0] All 0 R
Description
Descriptor Current Address
Specify the start address of descriptor processing.
Set a 16-byte boundary address value. When
descriptor processing is in progress, these bits
indicate the address of descriptor currently being
processed. After descriptor write-back, these bits
indicate the address of the next descriptor. When the
FEC DMAC enters the IDLE state after it has
processed the descriptor where the last flag is set,
this register indicates the address of the next
descriptor of the descriptor where the last flag is set.
Rev. 1.00 Nov. 14, 2007 Page 524 of 1262
REJ09B0437-0100