SH7670 Datasheet, PDF (536/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
Initial
Bit
Bit Name Value R/W Description
23 to 20 C[i]SO[3:0] All 0
R/W ^{Source Data Sequence}
Specify a swap method for reading data from memory such as the
STIF and SDRAM to the A-DMAC.
• When the source is not the STIF (C[i]SA bit = 0)
C[i]SO3: Data swap in two-byte units (longword swap in word
units)
0: As-is
1: Swap
C[i]SO2: Data swap in one-byte units (word swap in byte units)
0: As-is
1: Swap
C[i]SO1: Inversion of bit 1 at address when one or two bytes
are accessed
0: As-is
1: Inversion
C[i]SO0: Inversion of bit 0 at address when one byte is
accessed
0: As-is
1: Inversion
C[i]SO1 and C[i]SO0 function for endian adjustment. Note that
if an endian different from the endian of this LSI is used, up to
three different addresses are accessed from the address
where the start and end addresses are specified when an area
is allocated.
• When the source is the STIF (C[i]SA bit = 1)
C[i]SO3: Data swap in two-byte units (longword swap in word
units)
0: As-is
1: Swap
C[i]SO2: Data swap in one-byte units (word swap in byte units)
0: As-is
1: Swap
C[i]SO1: Data swap in one-bit units (byte swap in one-bit units)
0: As-is
1: Swap
C[i]SO0: Set this bit to 0 as reserved.
This bit is referenced in AES encryption/decryption,
DES/3DES encryption/decryption, SHA hash generation,
HMAC keyed hash generation, target data read for checksum
operation, and data copy from memory to the STIF and from
the STIF to memory. However, this bit is not referenced in key
copy and initial vector copy.
Rev. 1.00 Nov. 14, 2007 Page 510 of 1262
REJ09B0437-0100