SH7670 Datasheet, PDF (704/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
13
SOFR
0
R/W*⁷ Frame Number Refresh Interrupt Status*⁴
0: SOF interrupts not generated
1: SOF interrupts generated
(1) When the host controller function is selected
This module sets this bit to 1 on updating the
frame number when software has set the UACT
bit to 1. (This interrupt is detected every 1 ms.)
(2) When the function controller function is selected
This module sets this bit to 1 on updating the
frame number. (This interrupt is detected every 1
ms.)
This module can detect an SOFR interrupt
through the internal interpolation function even
when a damaged SOF packet is received from
the USB host.
12
DVST
0/1*¹
R/W*⁷ Device State Transition Interrupt Status*⁴*⁶
0: Device state transition interrupts not generated
1: Device state transition interrupts generated
When the function controller function is selected, this
module updates the DVSQ value and sets this bit to
1 on detecting a change in the device state.
When this interrupt is generated, clear the status
before this module detects the next device state
transition.
When the host controller function is selected, the
read value is invalid.
11
CTRT
0
R/W*⁷ Control Transfer Stage Transition Interrupt Status*⁴*⁶
0: Control transfer stage transition interrupts not
generated
1: Control transfer stage transition interrupts
generated
When the function controller function is selected, this
module updates the CTSQ value and sets this bit to
1 on detecting a change in the control transfer stage.
When this interrupt is generated, clear the status
before this module detects the next control transfer
stage transition.
When the host controller function is selected, the
read value is invalid.
Rev. 1.00 Nov. 14, 2007 Page 678 of 1262
REJ09B0437-0100