SH7670 Datasheet, PDF (589/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 15 Stream Interface (STIF)
Initial
Bit Bit Name Value R/W Description
4
PWMWP 0
R/W Setting this bit to 1 causes the selector 2 output to be
reflected in PWM.
Loading with this bit can be performed preferentially
without depending on the PWMSEL and PWMUEN
settings, except when the PWM control variable is an
invalid value as described in the UNZF bit field of STSTR.
If this bit is set to 1 together with the PWMWP bit,
PWMBWP takes precedence.
This bit is automatically cleared to 0.
3
STCRS
0
R/W Setting this bit to 1 causes the STC value to be
transferred to STSTC0R and STSTC1R.
This bit is automatically cleared to 0.
2
STCWP
0
R/W Setting this bit to 1 causes the STSTC0R and STSTC1R
values to be transferred to STC.
If the transfer conflicts with the data write after PCR is
received, the transfer using the write pulse of this register
takes precedence.
This bit is automatically cleared to 0.
1
PCRRS
0
R/W Setting this bit to 1 causes the PCR value to be
transferred to STPCR0R and STPCR1R.
This bit is automatically cleared to 0.
0
PCRWP 0
R/W Setting this bit to 1 causes the STPCR0R and STPCR1R
values to be transferred to PCR.
If the transfer conflicts with the data write after PCR is
received, the transfer using the write pulse of this register
takes precedence.
This bit is automatically cleared to 0.
Rev. 1.00 Nov. 14, 2007 Page 563 of 1262
REJ09B0437-0100