SH7670 Datasheet, PDF (667/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
Bit
Bit Name Initial Value R/W Description
1, 0
LNST[1:0] Undefined* R
USB Data Line Status Monitor
Indicates the status of the USB data bus lines (D+
and D-) as shown in table 17.6.
These bits should be read after setting DPRPU to 1
to notify connection when the function controller
function is selected; whereas after setting DRPD to 1
to enable pulling down the lines when the host
controller function is selected.
Note: * Depends on the DP and DM pin status.
Table 17.6 USB Data Bus Line Status
LNST[1]
LNST[0]
During Low-
Speed
Operation
(only when
Host
Controller
Function is
Selected)
During Full-
Speed
Operation
During High-
Speed
During Chirp
Operation
Operation
0
0
SE0
SE0
Squelch
Squelch
0
1
K state
J state
Not squelch Chirp J
1
0
J state
K state
Invalid
Chirp K
1
1
SE1
SE1
Invalid
Invalid
[Legend]
Chirp:
Squelch:
Not squelch:
Chirp J:
Chirp K:
The reset handshake protocol is being executed in high-speed operation enabled
state (the HSE bit in SYSCFG is set to 1).
SE0 or idle state
High-speed J state or high-speed K state
Chirp J state
Chirp K state
Rev. 1.00 Nov. 14, 2007 Page 641 of 1262
REJ09B0437-0100