SH7670 Datasheet, PDF (85/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 2 CPU
2.4.3 Arithmetic Operation Instructions
Table 2.12 Arithmetic Operation Instructions
Instruction
ADD
Rm,Rn
ADD
#imm,Rn
ADDC Rm,Rn
ADDV Rm,Rn
CMP/EQ #imm,R0
CMP/EQ Rm,Rn
CMP/HS Rm,Rn
CMP/GE Rm,Rn
CMP/HI Rm,Rn
CMP/GT Rm,Rn
CMP/PL Rn
CMP/PZ Rn
CMP/STR Rm,Rn
Instruction Code
Operation
Execu-
tion
Cycles
T Bit
Compatibility
SH2,
SH2E SH4 SH-2A
0011nnnnmmmm1100 Rn + Rm → Rn
1

Yes Yes Yes
0111nnnniiiiiiii Rn + imm → Rn
1

Yes Yes Yes
0011nnnnmmmm1110 Rn + Rm + T → Rn, carry → T 1
Carry Yes Yes Yes
0011nnnnmmmm1111 Rn + Rm → Rn, overflow → T 1
Over- Yes Yes Yes
flow
10001000iiiiiiii When R0 = imm, 1 → T
1
Com- Yes Yes Yes
Otherwise, 0 → T
parison
result
0011nnnnmmmm0000 When Rn = Rm, 1 → T
Otherwise, 0 → T
1
Com- Yes Yes Yes
parison
result
0011nnnnmmmm0010 When Rn ≥ Rm (unsigned), 1
1→T
Otherwise, 0 → T
Com- Yes
parison
result
Yes Yes
0011nnnnmmmm0011 When Rn ≥ Rm (signed),
1
1→T
Otherwise, 0 → T
Com- Yes
parison
result
Yes Yes
0011nnnnmmmm0110 When Rn > Rm (unsigned), 1
1→T
Otherwise, 0 → T
Com- Yes
parison
result
Yes Yes
0011nnnnmmmm0111 When Rn > Rm (signed),
1
1→T
Otherwise, 0 → T
Com- Yes
parison
result
Yes Yes
0100nnnn00010101 When Rn > 0, 1 → T
Otherwise, 0 → T
1
Com- Yes Yes Yes
parison
result
0100nnnn00010001 When Rn ≥ 0, 1 → T
Otherwise, 0 → T
1
Com- Yes Yes Yes
parison
result
0010nnnnmmmm1100 When any bytes are equal, 1
1→T
Otherwise, 0 → T
Com- Yes
parison
result
Yes Yes
Rev. 1.00 Nov. 14, 2007 Page 59 of 1262
REJ09B0437-0100