SH7670 Datasheet, PDF (146/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 5 Exception Handling
5.5 Interrupts
5.5.1 Interrupt Sources
Table 5.8 shows the sources that start up interrupt exception handling. These are divided into
NMI, user breaks, H-UDI, IRQ, PINT, and on-chip peripheral modules.
Table 5.8 Interrupt Sources
Type
NMI
User break
H-UDI
IRQ
On-chip peripheral module
Request Source
NMI pin (external input)
User break controller (UBC)
High-performance user debugging interface (H-UDI)
IRQ0 to IRQ7 pins (external input)
Direct memory access controller (DMAC)
Ethernet controller (EtherC)
Compare match timer (CMT)
Bus state controller (BSC)
Watchdog timer (WDT)
Encryption/decryption and forward error correction
core conjunction DMAC (A-DMAC)
Stream interface (STIF)
Host interface (HIF)
Serial sound interface_0 (SSI_0)
Serial sound interface_1 (SSI_1)
SD host interface (SDHI)
USB2.0 host/function module (USB)
I²C bus interface 3 (IIC3)
Serial communication interface with FIFO (SCIF)
Number of
Sources
1
1
1
8
16
1
2
1
1
7
2
2
1
1
3
1
5
16
Each interrupt source is allocated a different vector number and vector table offset. See table 6.4 in
section 6, Interrupt Controller (INTC), for more information on vector numbers and vector table
address offsets.
Rev. 1.00 Nov. 14, 2007 Page 120 of 1262
REJ09B0437-0100