SH7670 Datasheet, PDF (654/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
17.3 Register Description
Table 17.2 shows the register configuration of the USB. Table 17.3 shows the register state in each
processing mode.
Table 17.2 Register Configuration
Register Name
Abbreviation R/W Address
Access Connection
Size bus
System configuration control register SYSCFG
CPU bus wait setting register
BUSWAIT
R/W H'FFFF F800 16
R/W H'FFFF F802 16
Peripheral
bus
System configuration status register SYSSTS
R H'FFFF F804 16
Device state control register
DVSTCTR R/W H'FFFF F808 16
Test mode register
TESTMODE R/W H'FFFF
16
F80C
DMA0-FIFO bus configuration
register
D0FBCFG R/W H'FFFF F810 16
DMA1-FIFO bus configuration
register
D1FBCFG R/W H'FFFF F812 16
CFIFO port register
CFIFO
R/W H'FFFF F814 8/16/32
CFIFO port select register
CFIFOSEL R/W H'FFFF F820 16
CFIFO port control register
CFIFOCTR R/W H'FFFF F822 16
D0FIFO port select register
D0FIFOSEL R/W H'FFFF F828 16
D0FIFO port control register
D0FIFOCTR R/W H'FFFF F82A 16
D1FIFO port select register
D1FIFOSEL R/W H'FFFF
16
F82C
D1FIFO port control register
D1FIFOCTR R/W H'FFFF F82E 16
Interrupt enable register 0
INTENB0
R/W H'FFFF F830 16
Interrupt enable register 1
INTENB1
R/W H'FFFF F832 16
BRDY interrupt enable register
BRDYENB R/W H'FFFF F836 16
NRDY interrupt enable register
NRDYENB R/W H'FFFF F838 16
BEMP interrupt enable register
BEMPENB R/W H'FFFF F83A 16
SOF output configuration register SOFCFG
R/W H'FFFF
16
F83C
Interrupt status register 0
INTSTS0
R/W H'FFFF F840 16
Interrupt status register 1
INTSTS1
R/W H'FFFF F842 16
Rev. 1.00 Nov. 14, 2007 Page 628 of 1262
REJ09B0437-0100