SH7670 Datasheet, PDF (707/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 17 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
3
VALID
0
R/W*⁷ USB Request Reception
0: Not detected
1: Setup packet reception
When the host controller function is selected, the
read value is invalid.
2 to 0 CTSQ[2:0] 000
R
Control Transfer Stage
000: Idle or setup stage
001: Control read data stage
010: Control read status stage
011: Control write data stage
100: Control write status stage
101: Control write (no data) status stage
110: Control transfer sequence error
111: Setting prohibited
When the host controller function is selected, the
read value is invalid.
Notes: 1. This bit is initialized to B'0 by a power-on reset and B'1 by a USB bus reset.
2. These bits are initialized to B'000 by a power-on reset and B'001 by a USB bus reset.
3. This bit is initialized to 0 when the level of the VBUS pin input is high and 1 when low.
4. To clear the VBINT, RESM, SOFR, DVST, or CTRT bit, write 0 only to the bits to be
cleared; write 1 to the other bits. Do not write 0 to the status bits indicating 0.
5. A change in the status indicated by the VBINT and RESM bits can be detected even
while the clock supply is stopped (while SCKE is 0), and the interrupts are output when
the corresponding interrupt enable bits are enabled. Clearing the status through
software should be done after enabling the clock supply.
6. A change in the status of the RESM, DVST, and CTRT bits occur only when the
function controller function is selected; disable the corresponding interrupt enable bits
(set to 0) when the function controller function is selected.
7. Only 0 can be written to.
Rev. 1.00 Nov. 14, 2007 Page 681 of 1262
REJ09B0437-0100