SH7670 Datasheet, PDF (277/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 7 Bus State Controller (BSC)
(4) Single Read
A read access ends in one cycle when data exists in a cache-disabled space and the data bus width
is larger than or equal to the access size. As the SDRAM is set to the burst read with the burst
length 1, only the required data is output. A read access that ends in one cycle is called single read.
Figure 7.16 shows the single read basic timing.
CKIO
A25 to A0
A12/A11*¹
CSn
RASL, RASU
CASL, CASU
RD/WR
DQMxx
D31 to D0
BS
DACKn*²
Tr
Tc1
Td1
Tde (Tap)
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 7.16 Basic Timing for Single Read (CAS Latency 1, Auto Pre-Charge)
Rev. 1.00 Nov. 14, 2007 Page 251 of 1262
REJ09B0437-0100