SH7670 Datasheet, PDF (627/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 16 Serial Sound Interface (SSI)
16.3.5 SSI Clock Selection Register (SCSR)
SCSR is a 16-bit readable/writable register that selects the source of oversampling clocks used by
the SSI, as well as division ratio.
Bit: 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0













SSInCKS[2:0]
Initial Value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W
Note: n=0, 1
Bit
Bit Name
15 to 3 —
Initial
Value
All 0
2 to 0 SSInCKS[2:0] 000
Note: n = 0, 1
R/W Description
R Reserved
The read value is undefined. The write value should
always be 0.
R/W SSIchn Clock Select
Selects the source of the oversampling clock used by
SSIchn. See table 16.3.
Table 16.3 Selection of the Source for the Oversampling Clock Used by SSInCKS
SSInCKS[2:0]^*1 Clock Operating Mode
Setting
0 or 1
2
3
000
Reserved. This is given as an initial value and it should be changed to an
appropriate value before SSI operation.
001
Reserved
010
AUDIO_CLK input ^*2
011
AUDIO_CLK input ^*2/4
100
EXTAL input
CKIO input
Setting prohibited
101
EXTAL input /4
CKIO input /4
Setting prohibited
110
EXTAL input /2
CKIO input /2
Setting prohibited
111
EXTAL input /8
CKIO input /8
Setting prohibited
Note: *1. n = 0, 1
*2. Using AUDIO_CLK requires the setting of the control register of the corresponding port.
Rev. 1.00 Nov. 14, 2007 Page 601 of 1262
REJ09B0437-0100