SH7670 Datasheet, PDF (552/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
Bit
Bit Name
15 to 12 FECD00_DO[3:0]
Initial
Value R/W Description
All 0 R/W These bits function when the destination is read or
written.
FECD00_DO3:
Data swap in two-byte units (longword swap in
word units)
0: As-is
1: Swap
FECD00_DO2:
Data swap in one-byte units (word swap in byte
units)
0: As-is
1: Swap
FECD00_DO1:
Inversion of bit 1 at address when one or two
bytes are accessed
0: As-is
1: Inversion
FECD00_DO0:
Inversion of bit 0 at address when one byte is
accessed
0: As-is
1: Inversion
FECD00_DO1 and FECD00_DO0 function for
endian adjustment. Note that if an endian different
from the endian of this LSI is used, up to three
different addresses are accessed from the address
where the start and end addresses are specified
when an area is allocated.
Rev. 1.00 Nov. 14, 2007 Page 526 of 1262
REJ09B0437-0100