SH7670 Datasheet, PDF (1231/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 29 Electrical Characteristics
CKIO
A25 to A0
A12/A11^*1
Tr
Tc1
Tc2
Tc3
Tc4
t_AD1
t_AD1
Row
address
t_AD1
t_AD1
t_AD1
t_AD1
t_AD1
Column
address
WRIT command
t_AD1
t_AD1
CSn
RD/WR
RAS
CAS
DQMxx
D31 to D0
BS
t_CSD1
t_RWD1
t_RWD1
t_RASD1
t_RASD1
t_CASD1
t_DQMD1
t_WDD2
t_WDH2
t_BSD
t_CSD1
t_RWD1
t_CASD1
t_DQMD1
t_WDD2
t_WDH2
t_BSD
CKE
DACKn
TENDn^*2
t_DACD
(High)
t_DACD
Notes: 1. Address pin to be connected to A10 of SDRAM
2. The waveforms for DACKn and TENDn are produced when the active low state is specified.
Figure 29.27 Synchronous DRAM Burst-Write Bus Cycle (Equivalent to
Four Write Cycles) (Bank Active Mode: ACT+WRITE Commands, WTRCD = Zero Cycle,
TRWL = Zero Cycle)
Rev. 1.00 Nov. 14, 2007 Page 1205 of 1262
REJ09B0437-0100