SH7670 Datasheet, PDF (273/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 7 Bus State Controller (BSC)
(3) Burst Read
A burst read occurs in the following cases with this LSI.
• Access size in reading is larger than data bus width.
• 16-byte transfer in cache miss.
• 16-byte transfer by DMAC
This LSI always accesses the SDRAM with burst length 1. For example, read access of burst
length 1 is performed consecutively 4 times to read 16-byte continuous data from the SDRAM that
is connected to a 32-bit data bus. This access is called the burst read with the burst number 4.
Table 7.17 shows the relationship between the access size and the number of bursts.
Table 7.17 Relationship between Access Size and Number of Bursts
Bus Width
16 bits
32 bits
Access Size
8 bits
16 bits
32 bits
16 bits
8 bits
16 bits
32 bits
16 bytes*
Number of Bursts
1
1
2
8
1
1
1
4
Rev. 1.00 Nov. 14, 2007 Page 247 of 1262
REJ09B0437-0100