SH7670 Datasheet, PDF (158/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 6 Interrupt Controller (INTC)
Figure 6.1 shows a block diagram of the INTC.
IRQOUT
NMI
IRQ7 to IRQ0
PINT7 to PINT0
UBC
H-UDI
DMAC
CMT
BSC
WDT
MTU2
MTU2S
POE2
ADC
IIC3
SCIF
Input control
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
Priority
identifier
Com-
parator
Interrupt
request
SR
I3 I2 I1 I0
CPU
ICR0
ICR2
PINTER
IBCR
ICR1
IRQRR
PIRR
IBNR
IPR
IPR01, IPR02,
IPR05 to IPR14
Module bus
Bus
interface
INTC
[Legend]
UBC: User break controller
SDHI:
H-UDI: High-performance user debugging interface IIC3:
SD host interface
I2C bus interface 3
DMAC: Direct memory access controller
SCIF:
Serial communication interface with FIFO
CMT: Compare match timer
ICR0:
Interrupt control register 0
BSC: Bus state controller
ICR1:
Interrupt control register 1
WDT: Watchdog timer
ICR2:
Interrupt control register 2
EtherC: Ethernet controller
IRQRR:
IRQ interrupt request register
A-DMAC: DMAC with encryption/decryption
PINTER:
PINT interrupt enable register
and forward error correction core
PIRR:
PINT interrupt request register
HIF: Host interface
IBCR:
Bank control register
USB: USB2.0 host/function module
IBNR:
Bank number register
STIF: Stream interface
IPR01, IPR02, IPR05 to IPR14: Interrupt priority registers 01, 02,
SSI: Serial sound interface
05 to 14
Figure 6.1 Block Diagram of INTC
Rev. 1.00 Nov. 14, 2007 Page 132 of 1262
REJ09B0437-0100