SH7670 Datasheet, PDF (1263/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 29 Electrical Characteristics
29.4.15 STIF Module Signal Timing (1)
Table 29.21 STIF Module Signal Timing (1)
Conditions:
V_CC = V_CC (PLL) = DV12 = UV12 = 1.1 to 1.3 V, V_CCQ = DV33 = 3.1 to 3.5 V,
AV12 = 1.1 to 1.3 V, AV33 = 3.1 to 3.5 V,
V_SS = V_SS (PLL) = DG12 = UG12 = V_SSQ = DG33 = AG12 = AG33 = 0 V,
Ta = –20 to 70°C (regular specifications),
–40 to 85°C (wide temperature specifications)
Item
Symbol Min.
STn_CLKIN clock input Parallel mode
cycle
Serial mode
t
ST_CKIN_CYC
2
1.25
STn_CLKIN clock input Parallel mode t
0.4
ST_CKIN_H
high pulse width
Serial mode
0.4
STn_CLKIN clock input Parallel mode t_{ST_CKIN_L}
0.4
low pulse width
Serial mode
04
STn_CLKIN clock input Parallel mode t

ST_CKIN_r
rise time
Serial mode

STn_CLKIN clock input Parallel mode t

ST_CKIN_f
fall time
Serial mode

Note: * t_bcyc indicates the external bus clock (Bφ) cycle.
Max.
24
24
0.6
0.6
0.6
0.6
2.75
1.75
2.75
1.75
Unit
t_bcyc*
Figure
29.68
t
ST_CKIN_CYC
t_{ST_CKIN_CYC}
ns
ns
STn_CLKIN input
t_{ST_CKIN_CYC}
t_{ST_CKIN_H}
t_{ST_CKIN_L}
t_{ST_CKIN_H}
V_IH
V_IH
1/2 V_ccQ
V_IL
V_IL
V_IH
V_IH
1/2 V_ccQ
V_IL
t_{ST_CKIN_r}
t_{ST_CKIN_f}
t_{ST_CKIN_r}
Figure 29.68 STIF Module Signal Timing (1)
V_IL
t_{ST_CKIN_f}
Rev. 1.00 Nov. 14, 2007 Page 1237 of 1262
REJ09B0437-0100