SH7670 Datasheet, PDF (544/1292 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

Section 14 DMAC That Works with Encryption/Decryption and Forward Error Correction Core (A-DMAC)
Initial
Bit
Bit Name Value R/W Description
23 to 21 —
All 0 R Reserved
These bits are always read as 0. The write value should always
be 0.
20
FECC_DW 0
R/W "1 Descriptor Processing End" Interrupt Request Release Wait
E
Enable
When this bit is 1, the FEC DMAC ends processing of this
descriptor and enters the WAIT state unless FECC_DIE is 0
after write-back. If the "1 descriptor processing end" interrupt is
requested, the FEC DMAC waits for release of the interrupt
before it moves to processing of the next descriptor. If this
descriptor is the last descriptor when the interrupt is released,
the FEC DMAC ends processing and enters the IDLE state. If
this descriptor is not the last descriptor, the FEC DMAC reads
the next descriptor.
0: The FEC DMAC does not enter the WAIT state when the "1
descriptor processing end" interrupt is requested.
1: The FEC DMAC enters the WAIT state when the "1
descriptor processing end" interrupt is requested.
19 to 17 —
All 0 R Reserved
These bits are always read as 0. The write value should always
be 0.
16
FECC_DIE 0
R/W "1 Descriptor Processing End" Interrupt Request Enable
Specifies whether to enable or disable the "1 descriptor
processing end" interrupt request when processing of this
descriptor ends. Processing does not end even if this interrupt
is requested. This bit functions as the FECI_DI mask.
0: Disables the "1 descriptor processing end" interrupt request.
1: Enables the "1 descriptor processing end" interrupt request.
15 to 13 —
All 0 R Reserved
These bits are always read as 0. The write value should always
be 0.
Rev. 1.00 Nov. 14, 2007 Page 518 of 1262
REJ09B0437-0100